How to setup KC705-Yarr system

This document covers how to setup a KC705-Yarr system on CentOS 7.

Things to prepare

  • KC705 Evaluation Board
  • PC with CentOS 7 installed (tested with CentOS Linux release 7.4.1708)
  • Xilinx Vivado ver. 2016.2 (same as the development of YARR on XPressK7)

First compilation of the firmware

Project making on Vivado

#Download Yarr-on-KC705 source
git clone
cd Yarr-fw/
git checkout 0aa7b0dd18b77 #choose the latest commit on the kc705 branch.
git checkout -b yourname_dev
cd syn/kc705/
cd ../../../
source /opt/Xilinx/Vivado/2016.2/
vivado -mode batch -source create_yarr_FEI4_kc705_project.tcl

First compilation of the firmware

Start Vivado GUI

source /opt/Xilinx/Vivado/2016.2/

Open the created project above (named Yarr_FEI4_KC705)

  • A critical warning at the beginning… Is this really critical…?
  • [Project 1-19] Could not find the file ‘/home/hirose/work/KC705/TestSetup4/Yarr-fw/ip-cores/kintex7/mig_7series_0_kc705/mig_b.prj’.

Update IP cores

  • Tools->Report IP Status.
  • De-select mig_7series_0 and then update all IP cores (by the “Upgrade Selected” button).
  • A critical warning again…
  • [Coretcl 2-1279] The upgrade of ‘IP pcie_7x_0’ has identified issues that may require user intervention. Please review the upgrade log ‘/home/hirose/work/KC705/TestSetup4/Yarr_FEI4_KC705/ip_upgrade.log’, and verify that the upgraded IP is correctly configured.
  • Select mig_7series_0 and update. You’ll see an error message. This procedure is needed to proceed.
  • Then double-click on mig_7series_0 on the source tree to manually update the core.
  • Click “Next” on the first to fourth page (until a “Memory Selection” page).
  • At “Controller Options”, select “SODIMMs” for “Memory Type”.
  • Then click on “Create Custom Part”.
  • Make a custom part based on MT8JTF12864HZ-1G6. Change “Row Address” from 14 to 15.
  • At “Memory Options”, change “Input Clock Period” to “5000 ps (200 MHz)”, “RTT (nominal)” to “RZQ/6”.
  • At “FPGA Options”, change “Reference Clock” to “Use System Clock”, “System Reset Plarity” to “ACTIVE HIGH”, “IO Power Reduction” to “OFF”.
  • At “Extended FPGA Options”, check “DCI Cascade”.
  • At “IO Planning Options”, check “Fixed Pin Out”.
  • At “Pin Selection”, read a prepared XDC file (mig_7series_0.xdc), then validate it.
  • Click “Next” or “Generate” until the end…

BIT file generation

  • Click “Generate Bitstream” to generate a .bit file.

MCS file generation

  • Based on GUI…
  • Tools->Generate Memory Configuration File
  • Format: Memory Part: 28f00ap30t-bpi-x16
  • Filename: output_filename.mcs
  • Check “Load bitstream files”, and then choose your .bit file (it’s in Yarr_FEI4_KC705/Yarr_FEI4_KC705.runs/impl_1/top_level.bit by default).
  • (Check “Overwrite” if needed.)
  • or Based on TCL command (inside the vivado tcl console)…
  • write_cfgmem -format mcs -size 128 -interface BPIx16 -loadbit {up 0x00000000 “/path/to/your/bit/fileh/top_level.bit” } -file /path/to/your/mcs/file/20YYMMDD.mcs

Write configulation on your KC705

Add a memory device of KC705 in Vivado Hardware Manager

  • Right click on “Hardware window”, then “Add Configuration Memory Device”.
  • Memory type: 28f00ap30t-…

Install a device driver